This invention relates generally to signal processing, and more particularly to a method and system for determining frequency and time variations between electronic signals.
In signal processing applications, it is often necessary to determine certain parameters of a signal in order to accurately track the signal. These applications can include, but are not limited to, frequency control, symbol synchronization, bit synchronization and coherent carrier tracking. Phase-locked loops (PLLs) are well known in the art and they can function as a signal tracking tool. A PLL is an electronic circuit that can be configured to control an oscillator so that the oscillator produces a signal having a constant phase angle relative to a reference signal. A PLL can be configured to control a voltage controlled oscillator (VCO). In this regard, a variable tuning voltage can be applied to an input of the VCO to produce an output that varies over a wide frequency range. Notably, by applying a specified tuning voltage, the VCO can produce one or more signals having a particular frequency.
The resolution of a circuit can be used to define the variation between an input signal and a reference signal. In general, the smaller the variation between the input signal and the reference signal, the greater the accuracy or resolution. In contrast, the greater the variation between the input signal and a reference, the lesser the accuracy or resolution. Notably, less resolution will require less timing samples or counts to achieve synchronization. For example, a system that requires a 5% resolution or accuracy may require 128 counts to achieve such precision. However, a system that requires 0.03% accuracy may require 16,384 counts. In this context, a 5% accuracy provides less precision than a 0.03% accuracy or resolution. Importantly, the greater the required resolution, the greater the number of required counts and the greater the processing time. This greater processing time can adversely affect system speed and performance.
In certain applications, it can be critical to maintain a minimal resolution in order to maintain functionality of a circuit or particular integrated circuit (IC). For example, it can be necessary to switch a PLL from a first reference clock signal to a second reference clock signal. Under normal operation, the PLL will attempt to converge to the frequency of the first reference signal and once the desired accuracy is met, switching to the second reference signal can occur. However, if the frequency of the PLL and the second reference clock signal are not within a certain minimal resolution at the switchover point, signal divergence can result in a loss of synchronization, which can ultimately cause a loss of system functionality. To prevent divergence, greater resolution can be required.
Given these inflexibilities and other inherent drawbacks, there is a need for providing a method and circuit for determining variations between electronic signals in order to overcome the limitations described.
The invention provides a method for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal. The method can include the step of generating a plurality of time shifted input clock signals that are time shifted relative to the input clock signal. The plurality of time shifted signals can be sampled at periodic intervals relative to the reference clock signal. Sampled values for the time shifted signals can be compared with values for the reference clock to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal. The variation can include a condition wherein the frequency of the input clock signal can be less than the frequency of the reference clock signal, or the frequency of the input clock signal can be greater than the frequency of the reference clock signal, and the frequency of the input clock signal can be equal to the frequency of the reference clock signal.
The generating step can further include the step of shifting each of the plurality of time shifted signals by an amount equivalent to the period of the input clock signal divided by the number of input clock signals. The number of input clock signals includes the input clock signal and the time shifted versions of the input clock signal. The time shifted versions of the input clock signal can all have the same frequency.
The sampling step can further include the step of sampling at least one of the plurality of time shifted signals on a first rising edge of the reference clock signal to yield a first sampled value for at least one of the plurality of time shifted signals. A value for one or more of the time shifted signals can subsequently be stored in a flip-flop or register. The value for the one or more of the plurality of time shifted signals can be stored on a first falling edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal. Furthermore, one or more of the plurality of time shifted signals can be sampled on a second rising edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal to yield a second sampled value for one or more of the plurality of time shifted signals. Finally, the first and second sampled value for one or more of the plurality of time shifted signals can be compared to determine how the frequency of the input clock signal is varied from the frequency of the reference clock signal.
In another aspect of the invention, an electronic circuit can be provided for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal. The electronic circuit can include means for generating a plurality of time shifted input clock signals. The time shifted signals can be configured so that they can be shifted relative to the input clock signal. Means can be provided for sampling the plurality of time shifted signals at periodic intervals relative to the reference clock signal. Comparing means can be configured for comparing values for the sampled time shifted signals with values for the reference clock signal to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal. The variation can include a condition where the frequency of the input clock signal can be less than the frequency of the reference clock signal, the frequency of the input clock signal can be greater than the frequency of the reference clock signal, or the frequency of the input clock signal can be equal to the frequency of the reference clock signal.
The generating means of the electronic circuit can further include means for shifting each of the plurality of time shifted signals by an amount equivalent to the period of the input clock signal divided by the number of input clock signals. The number of input clock signals can include the input clock signal and the shifted versions of the input clock signals. The time shifted signals can be configured so that they can all have the same frequency.
The sampling means can further include means for sampling at least one of the plurality of time shifted signals on a first rising edge of the reference clock signal to yield a first sampled value for one or more of the plurality of time shifted signals. A flip-flop or register can be configured to store a value for one or more of the plurality of time shifted signals. The storing means can store the first sampled value of one or more of the plurality of time shifted signals on a first falling edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal. One or more of the plurality of time shifted signals can be sampled on a second rising edge of the reference clock signal occurring subsequent to the first rising edge of the reference clock signal, to yield a second sampled value for one or more of the plurality of time shifted signals. The comparing means can be configured to compare the first and the second sampled values for one or more of the plurality of time shifted signals, in order to determine the variation in frequency between the input clock signal and the reference clock signal.
In another aspect of the invention, a high resolution frequency detection circuit can be provided for determining variance between an input clock signal and a reference signal. The high resolution frequency detection circuit can include a first bank of flip-flops, a second bank of flip-flops, a third bank of flip-flops, and a fourth bank of flip-flops. Clock inputs of flip-flops in the first bank of flip-flops can be coupled to the reference clock signal and each data input of the flip-flops in the first bank of flip-flops can be singularly coupled to one of a plurality of time shifted input clock signals. Each data input of the flip-flops in the second bank of flip-flops can be singularly coupled to an output of each of the flip-flops in the first bank of flip-flops. Clock inputs of the flip-flops in the second bank of flip-flops can be coupled to a complement of the reference clock signal.
A first input of each XOR gate in a first bank of XOR gates can be singularly coupled to an output of one of the flip-flops in the first bank of flip-flops, while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops in the second bank of flip-flops. The XOR gates can be configured to compare a previously sampled value for an input clock signal with a successively sampled value for the input clock signal. A clock input of each of the flip-flops in the second bank of flip-flops can be coupled to a signal that is the complement of the reference clock signal. The high resolution frequency detection circuit can further include a log2(n) bit adder wherein each input of the log2M(n+1) bit adder can be singularly coupled to an output of one of the XOR gates in the first bank of XOR gates.
Another aspect of the invention can include a high resolution frequency detection circuit for determining variance between an input clock signal and a reference signal. In this regard, a clock input of each flip-flop in a first bank of flip-flops can be coupled to the reference clock signal and each flip-flop input can be singularly coupled to one of a plurality of time shifted input clock signals. Each input of flip-flops in a second bank of flip-flops can be singularly coupled to an output of each of the flip-flops in the first bank of flip-flops. A clock input of each flip-flop in the second bank of flip-flops can be coupled to a complement of the reference clock signal. Clock inputs of each of flip-flops in a third bank of flip-flops can be coupled to a signal that is the complement of the reference clock signal. Each input of the flip-flops in the third bank of flip-flops can be singularly coupled to one of a plurality of time shifted input clock signals. Each input for flip-flops in fourth bank of flip-flops can be singularly coupled to an output of each of the flip-flops in the third bank of flip-flops. Clock inputs of each of the flip-flops in the fourth bank of flip-flops can be coupled to the reference clock signal
A first input of each of XOR gate in a first bank of XOR gates can be singularly coupled to an output of one of the flip-flops of the first bank of flip-flops, while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops in the fourth bank of flip-flops. The XOR gates can be configured to compare a previously sampled value for an input clock signal with a successively sampled value for the input clock signal. A first input of each of the XOR gate in a second bank of XOR gates can be singularly coupled to an output of one of the flip-flops of the second bank of flip-flops, while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops of the third bank of flip-flops. Each of the XOR gates can be configured to compare a previously sampled value for an input clock signal with a successively sampled value for the input clock signal.
The high resolution frequency detection circuit can be configured so that a clock input of each of the flip-flops in the second bank of flip-flops can be coupled to a signal that is the complement of the reference clock signal. A clock input of each of the flip-flops in the fourth bank of flip-flops can be coupled to the reference clock signal. A first log2(n+1) bit adder can be configured so that each input of the first n-bit adder can be singularly coupled to an output of one of the XOR gates of The first bank of XOR gates. The high resolution frequency detection circuit can further include a second log2(n+1) bit adder configured so that each input of the first n-bit adder can be singularly coupled to an output of one of the XOR gates of the second bank of XOR gates.
In yet a further aspect of the invention, an enhanced resolution frequency detection circuit can be provided for determining the variance between an input clock signal and a reference signal. In this regard, the enhanced resolution frequency detection circuit can include a delay-locked loop having an input reference clock signal coupled thereto. A plurality of frequency detection circuits can be configured so that each clock input of the frequency detection circuits can be coupled to a separate output of the delay-locked loop. Each input of the frequency detection circuit can be coupled to a set of time shifted input clock signal. A plurality of XOR gates can be configured so that each of the plurality of XOR gates can be coupled to an output of each of the plurality of frequency detection circuits so as to provide an XOR operation of all bits in a same bit position at the output of each of the frequency detection circuit.
The invention also provides a time detection circuit for determining the variation between an input clock signal and a reference signal. The time detection circuit can include a first bank of n+1 flip-flops and a plurality of time shifted input clocksignals. Each of the time shifted input clock signals can be singularly coupled to a clock input of a flip-flop in the first bank of n+1 flip-flops. The reference clock signal can be coupled to an input of each of the n flip-flops in the first bank of flip-flops.